As computers and processors increase speed exponentially, the size of components, from chips to transistors, decreases.
One of the main problems with increased speed of processors, busses, and the like, is that higher operating speeds lead to an increased number of errors in data transmission. Accordingly, various schemes have been employed to detect and correct data errors. Among these schemes are parity checking and error correction and detection, or error correction code (ECC) schemes. Such schemes are known in the art, and will not be described further herein.
Parity checking allows only for the detection of a single bit error in a byte of data. Parity further consumes a fairly large amount of available real estate, and adds on the order of 10 to 15 percent to the cost of memory. Parity ensures reliability of data, but does nothing to improve data reliability. For these reasons, many manufacturers do not use parity checking for main memory, deeming it too expensive in cost and space for the benefits it provides.
ECC can not only determine the presence of a memory data error, but can also fix certain data errors without restarting the computer system. As bus widths and communication speed continue to increase, the comparative costs of ECC schemes become less expensive to implement than parity schemes. However, they do consume real estate and increase costs.
As bus sizes increase, the number of ECC bits traditionally required to fully protect the data increases as well. For a 128 bit data line, typical number of ECC bits required is on the order of 20 to 24 bits depending on the level of protection and correction desired. Further, for the L2 cache, this type of ECC scheme typically absorbs 10-15% of the available chip area. The requirement for upward of 20 or more ECC bits for a 128 bit data bus leads to a slowdown in performance.
When an error in data occurs, traditional solutions for the error is to flush the pipeline of the processor, and restart with fresh data. As processor and bus speeds increase, the solution of flushing the pipeline every time an error occurs would cripple the speed of the processor. To solve this problem, current processors use ECC schemes to prevent some of the slowdown which would be generated by the increased number of errors.
For example, the tag and data arrays of a secondary, or L2, cache, are often protected by ECC. Current schemes include a controller generating ECC bits, and doing ECC checking and error correction on the processor, using a backside bus to transmit 64 bits of data and 25 bits of tag information along with 8 ECC bits to an off-chip L2 cache. This scheme requires two core clock cycles during data return from the L2 cache to identify any problems. If more than one error occurs, the traditional solution of flushing the pipe is used. Another scheme places the L2 cache including tag and data arrays on the core processor. In this scheme, size of the L2 cache becomes an issue.
Speed of access to the L2 cache is also an issue. When the L2 cache sits off-chip, the tag lines routed within the chip consume significant real estate. All data accesses are routed through the bus to the off-chip array, leading to further performance slowdowns. The tag and data array components of a cache typically reside together on a chip, be it on the main chip, or off-chip, as in an L2 cache.